IBM 0.18um SOI RFCMOS Bandgap
(Silicon verified)
This work was done around 2014. First time to work on SOI process. Spent some time to read the PDK docs. Well, they are truly professional, at least for the documents.
Since customer wanted SOI RF SW integrated, SOI CMOS process is the choice. Also one cut is highly desired. I had little choice except humble parasitic PNP with opamp loop bandgap.
Not so clean schematic drawing since each device has 4 connections.
From left to right are
Enable circuits.
Constant Gm bias current. (some cap to enhance stability)
Startup circuits.
OPAMP and PTAP+VBE circuits.
After READY signal (blue) rise, VBG (read) followed. No overshooting or oscillating.
Difference between upper and lower curves are the zero TC setting. Upper one is taken at first cut.
Since customer wanted SOI RF SW integrated, SOI CMOS process is the choice. Also one cut is highly desired. I had little choice except humble parasitic PNP with opamp loop bandgap.
Not so clean schematic drawing since each device has 4 connections.
From left to right are
Enable circuits.
Constant Gm bias current. (some cap to enhance stability)
Startup circuits.
OPAMP and PTAP+VBE circuits.
Time domain startup response.
TC Behavior
Difference between upper and lower curves are the zero TC setting. Upper one is taken at first cut.
